Recently, in mobile electronic devices such as portable telephones, notebook-sized personal computers, PDAs and digital video cameras, which have been rapidly widespread, technology development for realizing small, thin and light devices has been rapidly advanced.
One principle electronic component for supporting this technology development is a semiconductor element. As the density of semiconductor elements is increased, the pitches and areas of electrode terminals have been reduced. Accordingly, strict requirements have been made with respect to a conductive bump used in flip-chip mounting a semiconductor element on a mounting board.
In this case, as the pitches of electrode terminals are narrowed, a short circuit between neighboring connection terminals on a mounting board occurs and a connection failure easily occurs between a conductive bump and an electrode terminal by stress that may be generated due to a difference in the thermal expansion coefficient between the semiconductor element and the mounting board.
In particular, the above-mentioned mobile electronic devices such as portable telephones may undergo shock when they are dropped. Therefore, when connection reliability between electrode terminals is insufficient, failure of the mobile electronic device may occur.
Furthermore, as the wiring rule of a semiconductor element becomes finer, the dielectric constant of an insulating layer formed on a semiconductor element is reduced and the insulating layer becomes porous. Therefore, when an Au bump and the like is mounted by a conventional flip-chip mounting, stress applied to the insulating layer below the Au bump may cause damage such as crack in the insulating layer.
On the other hand, in an area bump method for forming a conductive bump by using an entire surface on which a circuit is formed of a semiconductor element in order to avoid narrowing of pitches, high flatness of a mounting board is required in the entire mount area. In general, in the area bump method, firstly, a plurality of electrode terminals are formed on the semiconductor element and then a bump of solder, Au, or the like, is formed on the electrode terminals.
Next, bumps on the semiconductor element are allowed to face connection terminals formed on a circuit board, and the bumps on the electrode terminals are electrically bonded to the corresponding connection terminals, respectively. Furthermore, in order to improve electrical and mechanical bonding between the semiconductor element and the circuit board, a resin material is filled (under fill) between the semiconductor element and the circuit board.
However, in order to mount a next generation LSI whose number of electrode terminals is more than 5000 on a circuit board, it is necessary to form bumps corresponding to a narrow pitch of not more than 100 μm. However, it is difficult for current solder-bump formation technologies to do it.
Furthermore, it is necessary to form a large number of bumps corresponding to the number of electrode terminals. Therefore, in order to reduce the cost, high productivity is also required by reducing a mounting tact time per semiconductor element.
Conventionally, as the bump formation technology, a plating method, a screen printing method and the like have been used. The plating method is suitable for narrowing pitches but the step may become complicated, thus affecting productivity.
Furthermore, the screen printing method is excellent in productivity but has difficulty in narrowing pitches because the method uses a mask.
Under such circumstances, recently, technologies of selectively forming solder bumps on connection terminals of an LSI element or electrode terminals of a circuit board have been proposed. These technologies are not only suitable for forming fine bumps but also excellent in forming bumps at one time. Therefore, these technologies are receiving attentions as technologies suitable for mounting on boards of next generation LSI.
In the above-mentioned technology, firstly, a solder paste, which is made of a mixture of solder powder and flux and on the surface of which an oxide film is formed, is coated on the entire surface of the circuit board on which connection terminals are formed. Then, the circuit board is heated in this state, thereby melting the solder powder. As a result, a solder layer is selectively formed on the connection terminals without causing short circuits between the neighboring connection terminals (see, for example, patent document 1).
Another technology is carried out by coating a paste composition containing organic acid lead salt and metal tin as principle components on the entire surface of a circuit board on which connection terminals are formed, heating the circuit board to cause a substitution reaction of Pb and Sn, and allowing a Pb/Sn alloy to precipitate selectively on the connection terminal of the circuit board (see, for example, patent document 2 or non-patent document 1).
In still another technology, a circuit board on which an electrode is formed on the surface thereof is dipped in chemicals so as to form an adhesive film only on the surface of a connection terminal, and then solder powder is attached to the adhesive film, followed by heating and melting. Thus, a bump is selectively formed on the connection terminal (see, for example, patent document 3).
However, these technologies show a method for forming bumps on electrode terminals of a semiconductor element or connection terminals of a circuit board. In a general flip-chip mounting, after bumps are formed, a semiconductor element is mounted on a circuit board. A step of bonding between the connection terminal and the electrode terminal via a bump by a solder reflow and a step of injecting an under fill material between the circuit board and the semiconductor element to fix the semiconductor to the circuit board are needed. Therefore, production cost may be increased.
In order to solve such problems, a method for printing a conductive paste on the surface of a semiconductor element on which an electrode is formed via through holes of a printing screen, thereby forming a bump electrode at one time at a low cost is generally used (see, for example, patent document 4).
However, the conductive bump described in patent document 4 has the below-mentioned problems as described with reference to cross-sectional views shown in FIGS. 7A to 7E showing a method for forming a conductive bump by using a conductive paste.
Firstly, as shown in FIG. 7A, on the upper surface of semiconductor element 102 provided with a plurality of electrode terminals 101, printing screen 104 having openings 103 in positions corresponding to the plurality of electrode terminals 101 is disposed. Then, conductive paste 105 is placed on the upper surface of printing screen 104 and is pressed by squeegee 106. Thus, conductive paste 105 is printed on and filled in the surface of electrode terminal 101 from opening 103.
Next, as shown in FIG. 7B, by removing printing screen 104, conductive bump 105a is formed on electrode terminal 101 in a state in which a viscosity at the printing time is low. At this time, as shown in FIG. 7C, conductive bump 105a on electrode terminal 101 causes a dripping phenomenon around electrode terminal 101 over time due to a low viscosity, thus limiting the narrowing of pitches.
Next, as shown in FIG. 7D, semiconductor element 102 is reversed, positioned to electrode terminals 108 provided on the surface of circuit board 107, and flip-chip mounted thereon. At this time, as shown in FIG. 7E, in the case where semiconductor element 102 and circuit board 107 are tilted at the time of mounting, a non-uniform pressing power difference may occur so as to cause crush of the conductive bump. It is not possible to suppress the generation of non-uniform connection resistance due to short circuit 109 between neighboring electrode terminals 101 or connection failure portion 110 caused by the crush of the conductive bump.    [Patent document 1] Japanese Patent Application Unexamined Publication No. 2000-94179    [Patent document 2] Japanese Patent Application Unexamined Publication No. H1-157796    [Patent document 3] Japanese Patent Application Unexamined Publication No. H7-74459    [Patent document 4] Japanese Patent Application Unexamined Publication No. H11-274209    [Non-patent document 1] Electronics Packaging Technology, September 2000, pp 38-45